Program sequence information display device

ABSTRACT

An all electronic display device for sequentially displaying information. The information to be displayed is converted into the form of binary coded decimal pulses which are in turn converted into decimals in electronic form. By appropriate gating circuitry, the information is sequentially displayed during predetermined intervals of time and the information is updated at longer predetermined intervals of time.

. United States Patent [56] References Cited UNITED STATES PATENTS2,673,976 3/1954 Williams.....

3,041,595 6/1962 Caferro 3,041,596 6/1962 Caferro 3,166,742 1/1965Sherwin.. 3,320,585 5/1967 Hines Primary Examiner-Robert L. GriffinAssistant Examiner-Joseph A. Orsino, Jr.

Attorney-Kenyon & Kenyon Reilly Carr & Chapin [54] PROGRAM SEQUENCEINFORMATION DISPLAY DEVICE ABSTRACT: An all electronic display devicefor sequentially 12 Claims 3 D'awmg displaying information. Theinformation to be displayed is [52] 0.5. CI. 340/324, n r d in o h f rmof binary coded decimal pulses which 340/334 are in turn converted intodecimals in electronic form. By ap- [51] Int. Cl H05b 39/00 pr p e g ingircuitry, th information is sequentially dis- [50] Field of Search340/324, played during predetermined intervals of time and the infor-334 mation is updated at longer predetennined intervals of time.

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PATENTEDUET 5:911

SHEET 1 0F 2 Q\$ M Q arm WW @1 am W wink haw Q WM Y Q W 2 A F ys ;m i Vu 0 $0M a mu 3 w wwmw mmm a Nxm H H W 9 mm a 5 as La s um 9 a g Q om NMvm Mm mw QN 8 H v 8 I HNVXUDW llkll l VN ANN g wwl l ow gk m 08 Rm SQ QRT? 8 PROGRAM SEQUENCE INFORMATION DISPLAY DEVICE BACKGROUND OF THEINVENTION This invention relates to information display systems andparticularly to information display systems wherein it is desired tosequentially display infonnation at an arbitrary interval of time aswell as update the information to be displayed ata greater interval oftime. g v,

The use of display devices in the advertising as well as other media iswell known. These, however, have comprised either mechanical orelectromechanical display apparatus and have generally utilized cammechanisms and bulky switching devices. Typically, the display device ofthe prior art contained a plurality of bulky contact-swtiching devicesconnected to a display panel. These contacts were opened and closed tolight appropriate lamps on the display panel. A set of such contacts wasprovided for each type of information sought to be displayed and cammeans were provided to shift control of the lamps on the display panelbetween the sets of contacts corresponding to the various types ofinformation to be displayed, thereby providing'the desired sequence ofdisplay. The disadvantage of the prior art display devices reside intheir unwieldy size due partially to the bulky switching equipment andcam mechanism employed therein. In addition to their unwieldy size involume as well as in weight the prior art display devices are extremelycumbersome to repair. If a prior art display device was in need ofrepair only a skilled mechanic in the art with great difficulty and muchexpense could accomplish the repair. In addition, once a prior artdisplay device had been built to display time and temperature it wouldbe very cumbersome if not virtually impossible toalter the device todisplay time and a worded message or to control a traffic system. Itwould also be very difficult to alter the device to change the displaycycle frequency. Other disadvantages of prior art display devices residein the fact that the input power requirements are generally high; thatthey do not lend themselves readily to remote control operations; thatthey have at least some moving parts which, of course, increases themaintenance of the device and finally, the prior art display devicescontain many switches which can cause troublesome arcing and burning outof contacts.

SUMMARY OF INVENTION with these problems with prior art display devicesin mind, it is an object of my invention to provide a display devicewhich has no cam mechanisms or bulky switching devices.

It is a further object of my invention to provide a display device whichis all electronic.

It is a still further object of my invention to provide a display devicewhich is very compact and very light in weight.

It is a still further object of my invention to provide a display devicewhich is comprised of no moving parts.

It is a still further object of my invention to provide a display devicewhich can be repaired easily, inexpensively and by one unskilled in theart.

It is a still further object of my invention to provide a display devicein which either the type of information to be displayed can be changedor the timing cycle can be changed very easily, very inexpensively bysimply replacing a card of electronics.

It is a still further object of my invention to provide a display devicewhich can be adapted to sequentially display informa tion and/or used tocontrol a traffic light system and/or used to control any programsequence information display system.

These objects and others are achieved by my invention in which theinformation which is to be sequentially displayed is first convertedelectronically to binary coded decimal pulses. These binary codeddecimal pulses are electronically converted to decimal form, one set foreach set of information to be sequentially displayed. Each. set ofbinary coded decimal pulses is applied in sequence to a buffer unit inaccordance with strobe pulses applied to gates associated with each setof information to be displayed The output of the buffer unit isconverted electronically to pure decimal or alpha/numeric fonn which canbe applied to high or low level indicator units.

For a fuller understanding of the nature and objects of the invention,reference should be had to the following detailed description taken inconnection with the accompanying drawings in which:

FIG. I is a diagrammatic view of the complete mechanism which providesfor displaying the sequence of time and temperature displays on adisplay panel;

FIG. 2 is a view of the configuration of bulbs which can represent thenumerals from 0 to 9;

FIG. 3 is a view of the portion of the present invention which providesfor the control signals for regulating the timing of sequential display.

Referring now to the drawings, and to FIG. I in particular, my inventionis shown as embodied in a display mechanism adapted to measure andsequentially display time and temperature. The temperature is measuredby a temperature sensor indicated at 2. The temperature sensor 2 may beany conventional device which senses the temperature and converts thisinformation into an electric signal for use in display. For example, andby way of illustration, the temperature sensor 2 might be a singletransistor connected to an emitter follower through appropriatecircuitry. In that case the single transistor would be constrained tooperate in a range of linear change of base/emitter voltage with achange of temperature. This voltage would then be measured from thesingle transistor buffered by an emitter follower. This method oftemperature sensing is well known in the art and the values of theelements in the circuitry involved may be determined by methods wellknown in the art and will depend generally on the characteristics of thetransistors used as well as the temperature range to be measured, whichfor the purpose of the present illustration we may take to be from -20F. to +l99 F. Of course, this range is purely arbitrary and is used toillustrate the inventive concepts of my invention and should not beinterpreted as a limitation on its range of operation. For this.illustration of the temperature sensor 2, the voltage measured, is fedvia an emitter follower from the temperature sensor 2 to an analog todigital converter 4, a device well known in the art. The analog todigital converter 4 receives the signal from the temperature sensor 2and converts this analog signal to a sequential series of pulses thefrequency of which changes with the amplitude of the input signal. Inother words the output of the analogto digital converter is a linearfrequency approximation to the input signal. By way of illustration atypical analog to digital converter comprises an integrator,adiscriminator and a switch. The signal from the temperature sensor 2 isfed into the integrator which charges up a capacitive circuit. When thecapacitive circuit reaches a predetermined level, let us say 4 voltsbyway of illustration, this triggers the discriminator circuit whichfeeds back, through an electronic switch, a predetermined oppositecharge into the capacitive circuit. This opposite charge tends todischarge the capacitive circuit, turning the discriminator off andallowing the capacitive circuit to charge up again to the triggeringlevel. This cycle continues linearly and follows the input signal i.e.the frequency of the output pulses will increase and decrease with theinput voltage. The output pulses from the analog to digital converter 4are next led to a prescaler 5. The prescaler 5 scales down the frequencyof the pulses from the analog to digital converter 4 so that the outputof the prescaler 5- is a pulse train of frequency in cycles per secondequal to the temperature in degrees plus 20. The output pulses from theprescaler 5 are next led to a sample gate 6. The sample gate 6 'servestwo functions. First it acts as a gate wherein it will allow a firstsignal to pass through it only when it is activated by a second signalapplied to it Gating circuitry of this nature is generally known in theart. Secondly, the sample gate 6 shapes the pulses that it receives fromthe analog to digital converter 4. The output of this shaping circuitrycomprises well defined pulses of steeply rising and falling edges. Theoutput of the sample gate 6 is led into a negative/positive gate 8 alonginput wires designated as 8a. The pulses which are fed into thenegative/positive gate 8 along the input wires 8a are immediately fed toa negative temperature memory scaler through wires 8b. The negativetemperature memory sealer 10 starts with a count of 20 and then countsin a negative direction to zero. When the negative temperature memoryscaler 10 has reached a count of zero there is an electronic change overto a positive temperature memory scaler 12. The pulses which wereapplied to the negative/positive gate 8 through the wires 80 aretransferred from the negative temperature memory sealer 10 to thepositive temperature memory scaler 12. The positive temperature memorysealer 12 then continues to counting in a positive direction from zeroto +199 for the purposes of illustration. The electronic change overfrom the negative temperature memory scaler 10 to the positivetemperature memory scaler 12 may be accomplished in several equivalentways. By way of illustration, this change over may be accomplished bycausing the negative temperature memory sealer 10 to act as a shortcircuit with respect to the incoming pulses which enter negativetemperature memory scaler 10 through lines 8b. These pulses would thengo directly from line 8b to line 8c without further counting beingregistered in the negative temperature sensor. According to thepreferred embodiment of my invention, the pulses on wires 80 are routedthrough the negative/positive gate 8 and out again over wires 8d to thepositive temperature memory scaler 12 where the counting is registeredfrom zero to +199 in the illustration. Of course it would be equivalentifthe pulses on wires 80 were led directly into the positive temperaturememory scaler 12, thus bypassing the negative/positive gate 8 en routefrom the negative temperature memory sealer 10 to the positivetemperature memory sealer 12. Another possible method of effectuatingthe electronic change over when the negative temperature memory scaler10 reaches a count of zero, which is not shown would be to have thenegative temperature memory scaler 10, on the count of zero, re-routethe pulses coming in on the wires 8a into the negative/positive gate 8,which at the same time causes the pulses coming in on line 8a to godirectly to the positive temperature memory sealer 12 through wires 8d.To summarize the operation of the temperature memory scaler portion ofmy invention, it can be seen that the shaped pulses from the analog todigital converter 4 is a linear sequential train of pulses which is adirect representation of the output of the temperature sensor 2. Thesepulses are sampled by the sample gate 6 and gated by the sample gate 6to the negative temperature memory scaler 10. The negative temperaturememory scaler 10 consists of two reverse memory sealers, reverse in thesense that these sealers count backwards from a predetermined level aspulses are sent through it. The first reverse memory scaler has a scaleof 10 and the other reverse memory scaler has a scale of two. For therange of 20 F to +l99 F given in the present illustration, the negativetemperature memory scaler 10 is so arranged that when the first pulse ofthe sequential signals enters the negative temperature memory scaler 10on wires 8b the first reverse memory scaler counts the pulse and goesfrom zero to nine and at the same time the second negative memory scalergoes from zero to one, thus a reading of -l9 is seen on the output ofthe negative temperature memory scaler 10 after it has counted the firstpulse through it. The first and second reverse memory sealers are soconnected that the second will not receive pulses to count unless thefirst has a reading of zero. When the second pulse enters the negativetemperature memory scaler 10 on wires 8b the first reverse memory scalerwill receive it and its count will go from nine to eight but the secondreverse memory sealer will not receive the second pulse since the counton the first reverse memory scaler was not zero when the pulse enteredthe negative temperature memory scaler 10. Thus. the output of negativetemperature memory sealer 10 will be l8 after the second pulse. Onsucceeding pulses the first reverse memory scaler will run down througheight, seven, etc. to one and zero while the second reverse memoryscaler'will remain at one. On the very next pulse after the firstreverse memory scaler registers zero the first reverse memory scalerwill go from zero to nine and the second reverse memory scaler, becausethe first reverse memory scaler had registered a zero, will receive thepulse and go from one to zero. On succeeding pulses the first reversememory scaler will again run down through nine, eight, seven, etc. tozero. When the first reverse memory sealer has a count of zero therewill be a coincidence of a count of zero in both the first and secondreverse memory sealers. When this occurs the negative temperature memoryscaler 10 is adapted to ensure that the next pulse that it receives isnot counted by the negative temperature memory scaler 10 but is sent tothe positive temperature memory scaler 12 through the negative/positivegate 8. At the same time the negative temperature indicator signal whichhad been on wires 82 is switched to wires 8f and become a positivetemperature indicator signal. The positive temperature memory scaler 12is a conventional sealer of the type well known in the art. This scaleroperates in the reverse of the negative temperature memory scaler 10 andoperates in the upward counting direction. The positive temperaturememory sealer of this illustration with an upper temperature range of+199 F. has three conventional positive memory sealers with scales ofl0, l0 and two respectively. The first two sealers reset to zero at thecount of 10 and the third sealer resets to zero at the count of two. Theoutput of the negative temperature memory scaler 10 and the positivetemperature memory scaler 12 are in the form of binary coded decimalsand are gated respectively through gate 14 and gate 16. The output ofgate 14 is carried on wires 10a and 10b. Wires 10a carry the binarycoded decimal representation of the units of negative temperature andwires 10b carry the binary coded decimal representation of the lOs ofnegative temperature. The output of gate 16 is carried on wires 12a, 12band 12c. Wires 12a carry the binary coded decimal representation of theunits of positive temperature, wires 12b carry the binary coded decimalrepresentation of the tens of positive temperature and wires 12c carrythe binary coded decimal representation of the hundreds of positivetemperature. The wires 12a, 12b and 12c feed the binary coded decimalrepresentation of the temperature into a buffer gate 18. The function ofthe buffer gate 18 will become apparent shortly. Time is measured andprepared for display by a l2-hour-elock memory scaler 20. The l2-hour-clock memory scaler 20 received pulses at the rate of l pulse perminute from a controller unit 22 on wires 22a. The controller unit 22 isthe heart of the present invention and will be described in more detailbelow. The l2-hour-clock memory scaler comprises four memory sealers.The first memory scaler has a scale of 10 and resets to zero on a countof 10. The second memory scaler has a scale of six and resets to zero ona count of six. These two memory sealers register the minutes. The thirdmemory scaler has a scale of IO and resets to zero on a count of ID. Thefourth memory scaler has a scale of two and it is so adapted to act withthe third memory scaler such that the third and fourth memory sealersreset to one on a count of 13, hence giving a time change of from 12:59on the four memory sealers to 1:00 instead of 13:00. The output of thel2-hour-clock memory scaler is gated through gate 24 on wires 20a, 20b,20c, and 20d to the buffer gate 18. Wires 20a conducts the binary codeddecimal representation of the units of minutes and comprises four wires,Wires 20b conducts the binary coded decimal representation of the 10'sof minutes and comprises three wires. Wires 20c conducts the binarycoded decimal representation of the units of hours and comprises fourwires. Wires 20d conduct the binary coded decimal representation of the10's of hours and comprises one wire. The binary coded decimal outputsfrom the clock memory scaler 20 and from the negative and positivetemperature sealers 10 and 12 respectively must pass through the bufiergate 18. The buffer gate 18 performs two functions. First, it is capableof accepting. sequentially, information from the l2-hour-cloek memorysealers 20 on the onehand and the negative and positive temperaturememory sealers l0 and 12 respectively. Secondly, it converts each binarycoded decimal pulse from each decimal position into a nonambiguouscondition for decoding. For example, the output of the l2-hour-clockmemory sealer appearing on wires 20a represent in binary code the unitsof minutes. The wires 20a comprise four wires which represent 1, 2, 4 or8 when energized. Thus the decimal numbersfrom zero to nine can berepresented on wires 200 by energizing the appropriate wiresrepresenting l, 2, 4 and 8. The output of the buffer gate 18corresponding to the input on wires 20a let us say appears on wires 18a.Whereas wires 20a comprise four wires representing 1, 2, 4 and 8 thewires 18a comprise eight wires representing 1, T, 2, 2, 4, Z, 8 and i.In other words on wires 180 the lack of a 4 component, for example, isrepresented by a signal on wire 3 whereas the lack of a 4 component onwires 20a is represented by the lack of a signal on the wire 4. Thiseight wire method of decimal decoding is completely unambiguous becauseno combination of signals is ever repeated, whereas with a four wiremethod of decimal decoding of the digits 1 to 9 the combination ofsignals representing the digit 1 is included in the representation ofthe digits 1, 3, 5, 7, 9. The outputs of the buffer gate 18 are fed to adecimal decoder 26 along lines 18a, 18b, 18c and 18d as hereinabovedescribed. The decimal decoder converts the binary coded decimalrepresentation of each decimal position into its decimal form by methodsand devices well known in the art. For example, for each set of wires18a, 18b, 18c and 18d coming into the decimal decoder 26 from the bufiergate 18 there is a corresponding group of wires 26a, 26b, 26c, 26d eachwith 10 wires corresponding to the decimal numbers zero through nine. Soif on wires 18a, for example, the decimal to be represented is five,then the wires of 180 will have signals on the following wires: 1, 2, 4,3'. This particular input on wires 18a would cause the decimal decoder26 to produce a signal on that wire of wires 26a which corresponds tothe decimal. number five. The outputs of the decimal decoder-26 are fedinto an alpha/numeric decoder 28. The alpha/numeric decoder 28 is wellknown in the art. One can better understand the operation of thealpha/numeric decoder 28 by reference to FIG. 2 where in a configurationof lamps 30 are shown which comprisesseven lamps designated by 30a, 30b,30c, 30d, 30e, 30f and 30g. It can be seen from configuration 30 of FIG.2 that the numeral three can be displayed if lamps 30a, 30b, 30c, 30dand 30g are actuated. Thus, referring back to FIG. 1, for each set ofwires 26a, 26b, 26c, and 26d coming into the alpha/numeric decoder 28from the decimal decoder 26 there is a corresponding set of wires 28a,28b, 28c, and 28d each with seven wires corresponding to the sevenelements 30a through 30g of configuration 30 of FIG. 2 which are neededto represent any of the decimal numbers zero through nine. Then, asabove-described, if the output of the buffer gate 18 on wires 18a is thebinary coded decimal five then the wires 1,2, 4, will carry signals ofthe wires 18a. These signals will enter the decimal decoder 26 andproduce a signal on the wire representing the decimal five on the wires26a. This signal will enter the alpha/numeric decoder 28 and willproduce a signal on those wires of wires 284 which would correspond tothe elements 30a, 30f, 30g, 300 and 30d of the configuration 30 of FIG.2. The negative and positive temperature indicator signals on wires 8eand 8f are gated into the alpha/numeric decoder 28 through a gate 31. Ofcourse, the above description is by way of illustration only and itshould be fully realized that alpha/numeric decoders are readilyavailable in the art which could produce alphabetic and punctuation aswell as numerals. The present illustration of my invention is for asequential display of time and temperature but of course my invention isequally well adapted to sequentially display time and a message, forexample. In that case, an alpha/numeric decoder would be used which wascapable of coding into an alphabet, punctuation as well as numerals. Forthe purpose of the present illustration 1 have shown in FIG. 1 that theoutput of the alpha/numeric decoder 28 is fed to a low voltage driver32. The low voltage driver 32 has four discrete sections each adapted toreceiveone of the four decimal representations.

Each section is a transistor amplifier driven for indicators 34 such asData Lite or like indicators. For example, a positive voltage appearingon one of the wires of wires 28a, let us say the wire corresponding tothe lamp 30a of FIG. 2, will turn NPN transistors to saturation causinga current through lamp 30a. The lamp drive is through the NPNtransistors, the collectors of which are connected through the lamps toa positive potential, for example 24 volts. Of course, the outputs fromthe alpha/numeric decoder 28 could be fed into a high-voltage driver,not shown. Such a high-voltage driver is the Triac. A Triac is a newlydeveloped device that is energized by an alternating current andtriggered by a direct current. The Triac operates quite similarly to thelow-voltage driver 32 except that, although usually unnoticed, the lampsdo in actual fact extinguish as in a normal electric lamp. The Triac, aswell as switching high potentials, can pass heavy current and unlikerelays, are entirely noiseless in operation.

The above has been a detailed description of how temperature and-timeare measured, coded, decoded and prepared for display in the presentillustration of my invention. The most important aspect of my invention,however, resides in the method and means of controlling the cycle ofsequential display. This control is provided by the controller 22. A raw60 cycles from the line is fed into a shaper 36. The shaper 36 receivesthe line at about the 6 volt level. The sine waves of the line arechanged to sharp spikes which are required to activate the micrologic.Thus, the output of the shaper 36 comprises well defined pulses ofsteeply rising and falling edges. Shapers of this nature are readilyavailable in the art. The output of the shaper 36, the 60 cycle pulsesof steeply rising and falling edges, are fed into the controller 22. Thecontroller 22 comprises a plurality of micrologic scalers which are soarranged that when the controller 22 receives the 60 cycle pulses fromthe shaper 36 the controller 22 emits the following pulses for thepurpose of controlling the cycle of sequential display of time andtemperature as above-described, the controller 22 emits l clock pulseper minute of adequate duration on wires 22a to the l2-hourclock memorysealer 20. in addition, the controller emits calibration pulses on line22b at frequencies of 10 pulses per second and 1 pulse per second andpulses of other frequencies as needed to the 12-hourclock memory sealer20. Further, the controller 22 emits pulses every 12 seconds which areof 6 seconds duration on wires 22c to the gate 24 which allows the12-hour-clock memory sealer 20 display its count for 6 seconds every 12seconds. The controller 22 emits reset pulses of short duration once aminute to the temperature sealers l0 and 12 and the negative/positivegate 8 on wires 22d. The controller 22 so coordinates the reset" pulsesgenerated on wires 22d with the pulses generated on wires 22a so thatthe reset pulses are generated 6 seconds before the pulses on wires 22a.Further, the controller 22 so coordinates the reset" pulses generated onwires 22d with the pulses generated on wires 220 so that whenever apulse is generated on wires 22d a pulse is also generated on wires 22c.The controller 22 emits a sample" pulse of 1 second duration everyminute to the sample gate 6 on wires 22e. The controller 22 socoordinates the "sample" pulses generated on wires 222 with the pulsesgenerated on wires 22d so that the sample pulses are generated 1 secondafter the pulses generated on wires 22d. Further the controller 22coordinates the sample" pulses generated on wires 22e with the pulsesgenerated during a period when a pulse is generated on wires 220. Thiscoordination of the pulses generated on wires 22e with those generatedon wires 22c will ensure that whenever the temperature is being sampled"and updated once a minute by the generation of a pulse on wires 22e,time will be displayed by the gating pulses every 12 seconds which areof 6 seconds duration on wires 22f to the gate 14, the gate 16 and thegate 31 which allows the output of the negative temperature sealer 10,the output of the positive temperature scaler l2 and the outputs onwires 8e and 8f to be displayed for 6 seconds every l2 seconds. Thecontroller 22 so coordinates the pulses on wires 22f with the pulses onwires 22c so that when there is a pulse on wires 220 there will not be apulse on wires 22f and when there is a pulse on wires 22f there willbeno pulse on wires 220. This coordination by the controller 22 of thepulses generated on wires 220 with the pulses generated on wires 22fwill ensure that the time and temperature will be alternately displayedfor a duration of,6 seconds each. It is to be noticed that because ofthe coordination provided by the controller 22 that when the temperatureis being sampled time is being displayed and that when the l2-hour-clockmemory scaler 20 is receiving a pulse on line 22a to advance its outputby 1 minute the temperature will be displayed.

Referring now to FIG. 3 I will describe the controller 22 in moredetail. Line voltage of 60 cycles per second is applied to the shaper36. As described the shaper 36 changes the 60 cycle sinusoidal line into60 cycle pulses with rapidly rising and rapidly falling edges especiallyadapted to activate the micrologic portion of my invention. The shaper36 feeds these 60 cycle pulses into the controller 22 on wire 36a.Inside the controller. these 60 cycle per second pulses are fed to afrequency divider 38. The frequency divider 38 is constructed frommicrologic chips and has a construction well known in the art. Thefrequency divider 38 is so constructed that the output on the frequencydivider 38 appearing on wires 38a are pulses having one-sixth of thefrequency of the pulses fed into it on wires 36a. Therefore, the signalon wires 38a are pulses of frequency per second. in addition to beingfed into the frequency divider 38, the pulses on wires 36a are switchedinto a wire of wires 22b. These pulses are switched on the wires 22b tothe l2-hour-memory clock scaler for calibration purposes as hereinabovedescribed. The pulses on wires 38a are fed into a frequency divider 40.The frequency divider 40, like the frequency divider 38, is constructedfrom micrologic chips but unlike the frequency divider 38 is soconstructed that the output of the frequency divider 40 appearing onwires 40a is pulses of a frequency one-tenth of the pulses on wires 38a.Therefore, the pulses on wires 40a have a frequency of l cycle persecond. in addition to being fed into the frequency divider 40, thepulses on wires 38a are switched into a wire of wires 22b. These l cycleper second pulses are switched on the wires 22b to the l2-hour memoryclock scaler 20 for calibration purposes as hereinabove described. Theoutput of the frequency divider 40 is fed on wires 40a to a frequencydivider 42. The frequency divider 42 is essentially the same as thefrequency divider 38. The output of the frequency divider 42 is pulsesof frequency one-sixth of the frequency of the pulses on wires 40a.Therefore, the output of the frequency divider 40 are pulses offrequency 1 cycle per 6 seconds. In addition to being fed into thefrequency divider 42, the pulses on wires 40a are switched into a wireof wires 22b. These 1 cycle per 6 second pulses are switched on wires22b to the l2-hour-memory clock scaler 20 for calibration purposes ashereinabove described.

The output of the frequency divider 42 is fed on wire 42a to amicrologic flip-flop 44. The flip-flop 44 is connected through anoninverting high voltage OR gate 52 to micrologic flip-flops 46, 48 and50. The function of the OR" gate 52 is to produce an output of highpotential when either of its inputs are at a high potential and toproduce an output of a low potential when both of its inputs are at lowpotential. The micrologic flip-flops 44, 46, 48 and 50 are so connectedthat they count the pulses on wires 42a and reset to zero on a count of10. The flip-flop 44 registers the binary l and when it is in the on"state its pin e" is at a high potential and its pin d" is at a lowpotential. When flip-flop 44 is in the off state its pin "d" is at ahigh potential and its pin e" is at a low potential. The flip-flop 46registers the binary 2 and when it is in the on" state its pin d is at ahigh potential and its pin "e" is at a low potential. When flip-flop 46is in the "off" state its pin (1" is at a low potential and its pin 2"is at a high potential. The flip-flop 48 registers the binary 4 and whenit is in the "on" state its pin "e" is at a high potential and its pin"d" is at a low potential. When flip-flop 48 is in the off state its pin11" is at a high potential and its pin (2" is at a low potential. Theflip-flop 50 registers the binary 8 and when it is in the on state itspin "11 is at a high potential and its pin e" is at a low potential.When flip-flop 50 is in the "off" state its pin e" is at a highpotential and its pin d" is at a low potential. Assume that theflip-flops 44 and 50 are all in the ofF state. This would represent acount of zero. It can be seen that when the flip-flops 44 to 50 are inthe off" state that both of the inputs to the OR" gate 52 will be athigh potential. In other words pins "a" and b" ofOR" gate 52 will be athigh potential. Therefore, as hereinabove described, the output of theOR" gate 52 at pin 0" will be at high potential. This high potential atpin 0" of "OR" gate 52 is applied to pin 0" of flip-flop 50 and thuskeeps flip-flop 50 in a disabled state, i.e., unable to receive pulsesat pin "b" of flip-flop 50 and so pin d" of flip-flop 50 will be at alow potential. Thus flip-flop 46 will be held in an enabled statebecause a low potential on pin d" of flip-flop 50 will cause a lowpotential on pin c of flip-flop 46. Tracing through the successivepulses on wires 42a into the flip-flops 44 to 50, it can be seen that ona count of six, flip-flops 46 and 48 are in the "on" state. Whenflip-flops 46 and 48 are in the on" state the two inputs to the OR" gate52 are both at a low potential. Therefore, as hereinabove explained, theoutput of the OR" gate 52 at pin 0" must be at a low potential. Thisthen switches flip-flop 50 to an enabled state because pin 0" offlip-flop 50 will be at a low potential. The next count into flip-flop44 on wires 42a will put flip-flop 44 in an "on" state. Now flip-flops44, 46 and 48 are all in an on" state thus making a count of seven. Thenext pulse on wires 420 will put flip-flops 44, 46 and 48 all in ofF'states. However, before this occurs, the same pulse will put flip-flop50 in an on state (flip-flop 50 having been enabled by the precedingpulse). When flip-flop 50 is thus switched to an on state pin (1" offlip-flop 50 is at a high potential thus pin c" of flip-flop 46 is alsoat a high potential and is thereby disabled from receiving the nextpulse. The next pulse on wires 420 into flipflop 44 puts flip-flop 44into an on" state thus giving a total count of nine in the scalers (i.e.flip-flop 44 is in an on" state; flip-flop 46 is in an off state;flip-flop 48 is in an off state and flipflop 50 is in an on state). Thenext pulse on wires 42a into flip-flop 44 puts flipflop 44 into an offstate. The pulse from flip-flop 44 by passes flip-flop 46 (because itwas disabled by the previous pulse on wires 42a) and resets flip-flop 50to an off state. The flip-flops 44 to 50 are now all in the off stateand the cycle is then repeated.

It is to be noticed that pin d" of flip-flop 44, pin d of flipflop 46,pin e" of flip-flop 48 and pin e" of flip-flop 50 are all connected to alow voltage AND" gate 54. The function of the AND gate 54 is to producean output only when all of its inputs are at a low potential. Only at acount of nine will pin d of flip-flop 44, pin d of flip-flop 46, pin e"of flip-flop 48 and pin e of flip-flop 50 all be at a low potential.Therefore, the AND" gate 54 will be switched on and produce an outputpulse at a count of nine. At a count of l0 all of the flipflops 44 to 50are switched to the off" state and therefore pin d of flip-flop 44 willbe at a high potential and thus the AND" gate 54 will switch off again.So at a count of nine the "AND" gate 54 will produce a positive goingpulse on wires 22d which will remain at a predetermined positive levelfor 6 seconds until a count of 10 at which time the pulse will benegative going to ground. Thus the reset pulses on wires 22d areproduced as hereinabove described. It is the positive going edge ofthese pulses, occurring at a count of nine, which actuates the resetcircuitry. The output from the AND" gate 54, in addition to beingproduced on wires 22d are led to a gate 56. The output of gate 56 is apulse similar to the output of gate 54 except that it is the negativegoing edge of the pulse which actuates the 1 pulse per minute on theminute on the wires 22a. The output from the gate 56, in addition tobeing produced on wires 22a, is fed to a gate 58. In addition to thisinput to gate 58 there are three outputs from the frequency divider 42counts pulses at the rate of one per second and the 60. The output ofgate 60 is a pulse train with a period of l2 7 seconds; the first 6seconds at a positive potential and the second 6 seconds at a groundpotential. The output of the gate 60 is fed on wires 22f. In addition tobeing fed on wires 22/, the output of gate 60 is led to a gate 62. Theoutput of gate 62 is also a pulse train with a period of l2 seconds; thefirst 6 seconds at ground potential and the second 6 seconds at apositive potential. The output of gate 62 is fed on wires 220. Thiselectronic coordination of the pulses on wires 22] and wires 22cproduces the desired sequential display as hereinabove described. it isthus that the controller 22 controls the frequency and timing of thesampling of the information to be displayed as well as controls thetiming of the sequential display.

The foregoing is considered as illustrative only of the principles of myinvention. Further,since numerous modifications and changes will readilyoccur to those skilled in the art, it is not desired to limit theinvention to the exact construction and operation shown and described,and accordingly all suitable modifications and equivalents may beresorted to, falling within the scope of the invention as claimed.

What is claimed is:

l. A program sequence information display device comprising:

a plurality of electronic information sensing means to sense and convertthe information from each information source to be displayed into asequential series of pulses;

a plurality of electronic counting means to sample the sequential seriesof pulses from the information sensing means and to convert these pulsesinto a simultaneous binary coded decimal output;

a plurality of first gating means to allow the sequential series ofpulses from the information sensing means to be sampled by theelectronic counting means for a predetermined period of time;

a plurality of second gating means to allow the simultaneous binarycoded decimal output of the electronic counting means to be displayedfor a predetermined period of time;

a control means to actuate the first gating means and control thefrequency and timing of the sampling of the information sensing meansand to actuate the second gating means and control the frequency andtiming of the dis play of the output of the electronic counting means.

2. A program sequence information display device according to claim 1wherein the control means comprises a plurality of solid-state devicesto convert a line voltage which enters the control means into aplurality of pulse trains of varying frequency to actuate said first andsecond gating means.

3. A program sequence information display device according to claim 2wherein the plurality of solid-state devices comprises:

a shaping means to shape said line voltage and to generate thereinpulses of sharply rising and falling edges;

a plurality of frequency scaling means operatively connected to saidshaping means to receive said pulses of sharply rising and falling edgesand to produce said pulse train of varying frequencies. 7

4. A program sequence infomiation display device according to claim 3wherein the frequency scaling means comprises:

pulses from the plurality of flip-flops. 5. A program sequenceinformation display device according to claim 1 wherein the electronicinformation sensing means comprises:

measuring means for receiving the information to be displayed and forgenerating an analog electronic signal which varies in a predeterminedmanner with the information to be displayed;

converting means for receiving said analog electronic signal from saidmeasuring means and for generating a discrete electronic signal whichvaries in a predetermined manner with the information to be displayed.6. A program sequence information display device according to claim 5wherein the said measuring means is adapted to generate a continuousvariable voltage signal which varies with the information to bedisplayed in a predetermined manner and wherein the converting means isan analog to digital converter which received the said variable voltagesignal and generates a pulse train whose frequency varies proportionallyto the voltage of said continuous variable voltage signal.

7. A program sequence information display device according to claim 1wherein the said counting means comprises:

a plurality of scalers of various counting capacity adapted to receivepulses from the information sensing means; and

logic circuitry operatively connecting said scalers and adapted to haveeach scaler represent in count a decimal position of the information tobe displayed.

8. A program sequence information display device according to claim 7wherein the said scalers comprises a plurality of solid-state flip-flopsso arranged with solid-state logic circuitry that the scalerssequentially count pulses from the information sensing means anddisplays this count in binary coded decimal form.

9. A program sequence information display device according to claim 1wherein the first gating means comprises a solidstate AND gate toreceive pulses from the control means and from the information sensingmeans and to pass the pulser from the information sensing means throughto its output only when there is a coincidence of pulses into said AND"gate from said control means and said information sensing means.

10. A program sequence information display device according to claim 1wherein the second gating means comprises a solid-state AND gate toreceive pulses from the control means and from the counting means and topass the output from the counting means through to its output only whenthere is a coincidence of signals into said AND" gate from said controlmeans and said counting means.

1 l. A program sequence information display device according to claim 1wherein the first gating means comprises a solidstate device to receivepulses from the control means and to lead said pulses to the informationsensing means to actuate the output of said information sensing meanswhenever there is a pulse from said control means into said first gatingmeans.

12. A program sequence information display device according to claim 1wherein the second gating means comprises a solid-state device toreceive pulses from the control means and to lead said pulses to thecounting means to actuate the output of said counting means wheneverthere is a pulse from said control means into said second gating means.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3,611,34? Dated October 5, 1971 Inventor(s) Charles E. L. Gingell It iscertified that error appears in the above-identified patent and thatsaid Letters Patent are hereby corrected as shown below:

Column 6, line 64, after "generated" and before "during" insert --onwires 22c so that the pulses on wires 22s will be generated--.

Column 6, line 69, after "pulses" and before "every" insert --generatedon wires 22c. The controller 22 generates pulses--.

Column 8, line 6, change "and" to --to--.

Column 8, line 75, after "Q2" and before "counts" insert --which are fedto gate 58. The frequency divider I2--.

Signed and sealed this 18th day of April 1972.

(SEAL) fittest:

I'JDWARD ILFLIBTCII I, JR. ROBERT GOTTSCHALK attesting OfficerCommissioner of Patents ORM (10-69) USCOMM-DC $O375-P69 U 5 GOVERNMENTPRINTING OFFICE? l5, 0*35-334

1. A program sequence information display device comprising: a pluralityof electronic information sensing means to sense and convert theinformation from each information source to be displayed into asequential series of pulses; a plurality of electronic counting means tosample the sequential series of pulses from the information sensingmeans and to convert these pulses into a simultaneous binary codeddecimal output; a plurality of first gating means to allow thesequential series of pulses from the information sensing means to besampled by the electronic counting means for a predetermined period oftime; a plurality of second gating means to allow the simultaneousbinary coded decimal output of the electronic counting means to bedisplayed for a predetermined period of time; a control means to actuatethe first gating means and control the frequency and timing of thesampling of the information sensing means and to actuate the secondgating means and control the frequency and timing of the display of theoutput of the electronic counting means.
 2. A program sequenceinformation display device according to claim 1 wherein the controlmeans comprises a plurality of solid-state devices to convert a linevoltage which enters the control means into a plurality of pulse trainsof varying frequency to actuate said first and second gating means.
 3. Aprogram sequence information display device according to claim 2 whereinthe plurality of solid-state devices comprises: a shaping means to shapesaid line voltage and to generate therein pulses of sharply rising andfalling edges; a plurality of frequency scaling means operativelyconnected to said shaping means to receive said pulses of sharply risingand falling edges and to produce said pulse train of varyingfrequencies.
 4. A program sequence information display device accordingto claim 3 wherein the frequency scaling means comprises: a plurality ofsolid-state flip-flops to count said sharply rising and falling pulsesand to generate a pulse after a preset number of counted pulses; solidstate logic circuitry operatively connecting said solid-state flip-flopsto establish the number of said sharply rising and falling input pulsesbetween successive output pulses from the plurality of flip-flops.
 5. Aprogram sequence information display device according to claim 1 whereinthe electronic information sensing means comprises: measuring means forreceiving the information to be displayed and for generating an analogelectronic signal which varies in a predetermined manner with theinformation to be displayed; converting means for receiving said analogelectronic signal from said measuring means and for generating adiscrete electronic signal which varies in a predetermined manner withthe information to be displayed.
 6. A program sequence informationdisplay device according to claim 5 wherein the said measuring means isadapted to generate a continuous variable voltage signal which varieswith the information to be displayed in a predetermined manner andwherein the converting means is an analog to digital converter whichreceived the said variable voltage signal and generates a pulse trainwhose frequency varies proportionally to the voltage of said continuousvariable voltage signal.
 7. A program sequence information displaydevice according to claim 1 wherein the said counting means comprises: aplurality of scalers of various counting capacity adapted to receivepulses from the information sensing means; and logic circuitryoperatively connecting said scalers and adapted to have each scalerrepresent in count a decimal position of the information to bedisplayed.
 8. A program sequence information display device according toclaim 7 wherein the said scalers comprises a plurality of solid-stateflip-flops so arranged with solid-state logic circuitry that the scalerssequentially count pulses from the information sensing means anddisplays this count in binary coded decimal form.
 9. A program sequenceinformation display device according to claim 1 wherein the first gatingmeans comprises a solid-state ''''AND'''' gate to receive pulses fromthe control means and from the information sensing means and to pass thepulser from the information sensing means through to its output onlywhen there is a coincidence of pulses into said ''''AND'''' gate fromsaid control means and said information sensing means.
 10. A programsequence information display device according to claim 1 wherein thesecond gating means comprises a solid-state ''''AND'''' gate to receivepulses from the control means and from the counting means and to passthe output from the counting means through to its output only when thereis a coincidence of signals into said ''''AND'''' gate from said controlmeans and said counting means.
 11. A program sequence informationdisplay device according to claim 1 wherein the first gating meanscomprises a solid-state device to receive pulses from the control meansand to lead said pulses to the information sensing means to actuate theoutput of said information sensing means whenever there is a pulse fromsaid control means into said first gating means.
 12. A program sequenceinformation display device according to claim 1 wherein the secondgating means comprises a solid-state device to receive pulses from thecontrol means and to lead said pulses to the counting means to actuatethe output of said counting means whenever there is a pulse from saidcontrol means into said second gating means.